https://gcc.gnu.org/g:516e4790f71ffd1d202912ec5162e79fee809d08
commit r15-10332-g516e4790f71ffd1d202912ec5162e79fee809d08
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Tue Sep 16 00:27:37 2025 +0000
Daily bump.
Diff:
---
gcc/ChangeLog | 40 ++++++++++++++++++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/ada/ChangeLog | 22 ++++++++++++++++++++++
gcc/cp/ChangeLog | 9 +++++++++
gcc/testsuite/ChangeLog | 32 ++++++++++++++++++++++++++++++++
5 files changed, 104 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b91d292bd10e..19b7dc95e137 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,43 @@
+2025-09-15 Kyrylo Tkachov <ktkac...@nvidia.com>
+
+ Backported from master:
+ 2025-09-03 Kyrylo Tkachov <ktkac...@nvidia.com>
+
+ PR target/121749
+ * config/aarch64/aarch64-simd.md (aarch64_<shrn_op>shrn_n<mode>):
+ Use aarch64_simd_shift_imm_offset_<vn_mode> instead of
+ aarch64_simd_shift_imm_offset_<ve_mode> predicate.
+ (aarch64_<shrn_op>shrn_n<mode> VQN define_expand): Likewise.
+ (*aarch64_<shrn_op>rshrn_n<mode>_insn): Likewise.
+ (aarch64_<shrn_op>rshrn_n<mode>): Likewise.
+ (aarch64_<shrn_op>rshrn_n<mode> VQN define_expand): Likewise.
+ (aarch64_sqshrun_n<mode>_insn): Likewise.
+ (aarch64_sqshrun_n<mode>): Likewise.
+ (aarch64_sqshrun_n<mode> VQN define_expand): Likewise.
+ (aarch64_sqrshrun_n<mode>_insn): Likewise.
+ (aarch64_sqrshrun_n<mode>): Likewise.
+ (aarch64_sqrshrun_n<mode>): Likewise.
+ * config/aarch64/iterators.md (vn_mode): Handle DI, SI, HI modes.
+
+2025-09-15 Georg-Johann Lay <a...@gjlay.de>
+
+ Backported from master:
+ 2025-09-15 Georg-Johann Lay <a...@gjlay.de>
+
+ * config/avr/avr-mcus.def: Add avr32eb14, avr32eb20,
+ avr32eb28, avr32eb32.
+ * doc/avr-mmcu.texi: Rebuild.
+
+2025-09-15 Xi Ruoyao <xry...@xry111.site>
+
+ Backported from master:
+ 2025-09-15 Xi Ruoyao <xry...@xry111.site>
+
+ PR target/121906
+ * config/loongarch/loongarch.md (*bstrins_<mode>_for_ior_mask):
+ Always create a new pseudo for the input register of the bstrins
+ instruction.
+
2025-09-11 Richard Sandiford <rdsandif...@googlemail.com>
PR rtl-optimization/121757
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 7545e0923ebf..fed526bc14b6 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250915
+20250916
diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog
index a91643769db3..2f771aa4e835 100644
--- a/gcc/ada/ChangeLog
+++ b/gcc/ada/ChangeLog
@@ -1,3 +1,25 @@
+2025-09-15 Eric Botcazou <ebotca...@adacore.com>
+
+ * gcc-interface/trans.cc (gnat_to_gnu)
+ <N_Object_Renaming_Declaration>: Deal with objects whose elaboration
+ is deferred.
+ (process_freeze_entity): Deal with renamed objects whose elaboration
+ is deferred.
+
+2025-09-15 Eric Botcazou <ebotca...@adacore.com>
+
+ * checks.adb (Apply_Discriminant_Check): Remove undocumented test
+ on Is_Aliased_View applied to the left-hand side to skip the check
+ in the case where the subtypes are the same, and replace it with a
+ test that the subtypes are constrained.
+
+2025-09-15 Eric Botcazou <ebotca...@adacore.com>
+
+ * exp_util.adb (Finalize_Address): In an untagged derivation, call
+ Root_Type on the full view of the base type if the partial view is
+ itself not a derived type.
+ (Is_Untagged_Derivation): Minor formatting tweak.
+
2025-09-11 Gary Dismukes <dismu...@adacore.com>
* exp_aggr.adb (Build_Container_Aggr_Code.Build_Size_Expr): In the case
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 0e20285553d9..201e2a53dee0 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,12 @@
+2025-09-15 Matthias Kretz <m.kr...@gsi.de>
+
+ Backported from master:
+ 2025-09-09 Matthias Kretz <m.kr...@gsi.de>
+
+ PR c++/121801
+ * mangle.cc (write_real_cst): Handle 16-bit real and assert
+ that reals have 16 bits or a multiple of 32 bits.
+
2025-09-12 Patrick Palka <ppa...@redhat.com>
Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index fc690a38ea2e..ab5e8a87f6c6 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,35 @@
+2025-09-15 Kyrylo Tkachov <ktkac...@nvidia.com>
+
+ Backported from master:
+ 2025-09-03 Kyrylo Tkachov <ktkac...@nvidia.com>
+
+ PR target/121749
+ * gcc.target/aarch64/simd/pr121749.c: Use dg-assemble directive.
+
+2025-09-15 Kyrylo Tkachov <ktkac...@nvidia.com>
+
+ Backported from master:
+ 2025-09-03 Kyrylo Tkachov <ktkac...@nvidia.com>
+
+ PR target/121749
+ * gcc.target/aarch64/simd/pr121749.c: New test.
+
+2025-09-15 Xi Ruoyao <xry...@xry111.site>
+
+ Backported from master:
+ 2025-09-15 Xi Ruoyao <xry...@xry111.site>
+
+ PR target/121906
+ * gcc.target/loongarch/pr121906.c: New test.
+
+2025-09-15 Matthias Kretz <m.kr...@gsi.de>
+
+ Backported from master:
+ 2025-09-09 Matthias Kretz <m.kr...@gsi.de>
+
+ PR c++/121801
+ * g++.dg/abi/pr121801.C: New test.
+
2025-09-12 Patrick Palka <ppa...@redhat.com>
Backported from master:
