> Thanks to reporting and testing. I've added different vlen variants to > my qemu-riscv64 CI runs and this kind of bug should not pass anymore.
Nice! FWIW Another common mistake is with tail agnostic bits. Running qemu with -cpu rvv_ta_all_1s/rvv_ma_all_1s=true/false may help find these. Using our Ascalon qemu model (with -cpu tt-ascalon) is also an option. We have different VLEN and TA behaviour than the qemu defaults. I'd love to add an option to qemu like -cpu rva23s64,randomize=true to test different implementation options like these. Anyway, thanks again! Mikey _______________________________________________ Gcrypt-devel mailing list [email protected] https://lists.gnupg.org/mailman/listinfo/gcrypt-devel
