Steven Wilson wrote:
I've never seen a dump list with memories included.
Okay. Well, I'd at least like to have the option. So, I'll file that
as an enhancement request.
The format is really only designed to dump "vectors."
But, rf[0] *is* a vector. I can understand not dumping it by default,
but if I explicitly list it, I really want it.
In addition, why won't rf[0] show up when I put it in a $monitor statement?
Finally, how do I grab a slice of rf[0] aka rf[0][15:12] ? Do I have to
wire *that* out and then slice the wire? I'm probably going to have to
build a parameterized register file module if I want
rf[someWire[2:0]][15:12]? This is nuts.
Why do register arrays not behave like an array of registers? Is this
in the standard somewhere or is everybody just following bugs in Verilog-XL?
-a
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