> Anyone ever come across design rules on minimum hole spacing which
> is more strict that just the minimum copper width?
Also, there's no reason why a via can't have a bigger-than-minimum
copper. I vote for "let it overlap, check drill spacing in drc".
However, I'd like to think about how we add new DRC parameters in pcb
first, rather than just make that list of anonymous numbers longer.
Can we use the Attribute() feature for these now? That lets us add as
many as we want, without changing the file format, in a
backwards-compatible (at least, future changes will be backwards
compatible) way. I.e.
Attribute("DRC::min-hole-hole-spacing" "15mil")
Attribute("DRC::min-hole-edge-spacing" "25mil")
Attribute("DRC::min-via-annulus" "10mil")
As long as we don't complain about parameters we don't understand, pcb
can support newer-than-expected boards.
Plus, this lets us read a vendor DRC file more easily.
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