Lennert Buytenhek wrote: it seems that submodule_rising becomes 1'b1 at t=1, so
somehow it is picking up a posedge clk at t=0.
I see it defined at time zero in two ways -- wire from sub and reg inside sub. Maybe one is X at t=zero?
topmodule_rising does _not_ seem to pick up a posedge clk at t=0, so that signal _does_ only become 1'b1 at t=11.
topmodule_rising is defined a 1 at t=zero and stays 1, so no edge. John Griessen _______________________________________________ geda-dev mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
