Hi, I'm trying to use iverilog to simulate my design to try and avoid using the piggish project navigator as much as possible however I am having trouble with the Xilinx primitives, eg..
[inchoate 21:52] ~/work/fpga/SA > iverilog -y . -y $XILINX/verilog/src/unisims -y $XILINX/verilog/src/XilinxCoreLib -tfpga SA_test2.v /usr/local/Xilinx/verilog/src/unisims/DCM.v:45: syntax error /usr/local/Xilinx/verilog/src/unisims/DCM.v:45: error: syntax error in parameter list. /usr/local/Xilinx/verilog/src/unisims/DCM.v:46: syntax error /usr/local/Xilinx/verilog/src/unisims/DCM.v:46: error: syntax error in parameter list. /usr/local/Xilinx/verilog/src/unisims/DCM.v:47: syntax error /usr/local/Xilinx/verilog/src/unisims/DCM.v:47: error: syntax error in parameter list. /usr/local/Xilinx/verilog/src/unisims/DCM.v:49: syntax error /usr/local/Xilinx/verilog/src/unisims/DCM.v:49: error: syntax error in parameter list. ... Lines 45-50 of the file are.. parameter real CLKDV_DIVIDE = 2.0; parameter integer CLKFX_DIVIDE = 1; parameter integer CLKFX_MULTIPLY = 4; parameter CLKIN_DIVIDE_BY_2 = "FALSE"; parameter real CLKIN_PERIOD = 10.0; // non-simulatable parameter CLKOUT_PHASE_SHIFT = "NONE"; I see here http://asics.chuckbenz.com/XilinxEDK_XPSquickstartforverilog.html someone getting an EDK derived design working and my design is much simpler than that so I am wondering if I'm missing something obvious. Thanks. -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C
signature.asc
Description: This is a digitally signed message part.
_______________________________________________ geda-dev mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
