On Sat, 2009-01-03 at 10:57 -0500, Paul Tan wrote: > Hi Peter Clinton, > > Thank you very much for you response, I really > appreciate it. > > I am a bit confused, after reading about Steve > Meier's "hierarchical bus".
I've never actually run the code, so I can't comment. I would be interested to hear more about it though. I'm especially interested in what attributes Steve's system uses to describe the buses being connected, since other than checking connectivity, for it to be useful I presume there needs to be some description of the bus's width, and end-points, along with some way of mapping it onto either pins on a chip, or circuitry inside a module. I didn't set out to support full netlisting of buses this release cycle. Ales just pointed out that gnetlist isn't making the distinction between bus pins and net pins, so is inadvertently making these bus pin connections part of the netlist already! I'm going to fix gnetlist to avoid adding bus-pins to the _net_list, but wondered if some backends might choose to import a module which is able to take the bus connectivity and flatten it according to some attribute based description of its contents, as expressed as nets. Steve, can you send an example design? -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) _______________________________________________ geda-dev mailing list geda-dev@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
