Hi John and Al, gnet-vhdl.scm, gnet-vams.scm and gnet-systemc.scm (all are stocked gEDA scheme files) used similar strategy as in gnet-verilog.scm to adapt to VHDL and SystemC specific netlisting requirement. So if gnucap or verilog-AMS has different requirement than the Standard Verilog netlisting, it can be easily adapted too.
Best Regards, Paul Tan -----Original Message----- From: John Griessen <j...@ecosensory.com> To: gEDA developer mailing list <geda-dev@moria.seul.org> Sent: Sat, 10 Jan 2009 9:13 pm Subject: gEDA-dev: gnet-verilog.scm -- testing it, readying it for gnucap netlisting I've been looking this scheme program over and don't see the concept of namespaces used all the way through as in the C++ example Al mentioned today on geda irc. Some pieces of netnames are found, but not named with a namespace prefix afterwards. (define verilog:identifier? uses regexpressions to find bit-range, single-bit, simple-id matches and classifies those as verilog:identifier? The whole program has lots of detail, so I think of creating a test suite as I go about creating and feeding it gschem schematics similar to the example of busses Dan gave here: http://archives.seul.org/geda/dev/Jul-2006/msg00039.html. I haven't done a test suite yet, so would like hints on doing a Makefile so I can run make test to process the example schematic and check for correct netlist output. Dan? Thanks, John _______________________________________________ geda-dev mailing list geda-dev@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev _______________________________________________ geda-dev mailing list geda-dev@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
