> Hi, > > [EMAIL PROTECTED] wrote: > > > I was thinking of building a huge macro library and > > adding a netlister for EDIF. But it would take away > > all the flexibility of HDL in the design. Just as you > > have sayed. > > If you can get your hands on the ViewLogic macro schematic library for your > Atmel devices, the tools `smash_megafile' and `convert_sym' can extract the > individual > symbols from the archive, and convert them to gEDA format respectively. > That should ease the creation of your macro library substantially. .. > > At the moment, the attribute translation is a bit rough, but that can be > fixed. Then all that remains, is the EDIF 2 0 0 netlister.... > Thanks for the hint, but I am afraid I would run into copyright problems than. Thomas > -- > -------------------------------------------------- > Mike Jarabek > FPGA/ASIC Designer > http://www.playground.net/~mjarabek > -------------------------------------------------- > > > >
