[EMAIL PROTECTED] said: > Say what? You can tie a reg variable to the output port of a module - > do it all the time? We are misunderstanding, I think. module foo (clk, d,q); input d,clk; output q; reg q; always @(posedge clk) q <= d; endmodule That is fine. There error is here: module main; reg clk, d; reg q; foo u1(clk, d, q); endmodule In this example, the reg q is connected to the output of the instance. This example is in error because of main.q, not main.u1.q. Right? Inside the module, reg variables cannot be connected to input or inout ports. For example, d and clk in module foo cannot be reg variables. -- Steve Williams "The woods are lovely, dark and deep. [EMAIL PROTECTED] But I have promises to keep, [EMAIL PROTECTED] and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."
