On Sun, 29 Jul 2001, Stephen Williams wrote: > [EMAIL PROTECTED] said: > > Simulators too big for VVMs output to be compiled is compiling no > > problem within a few seconds and run times aren't too bad at this > > point. > > That was the whole point of the entire 0.5 development cycle. It's > good to hear that someone has noticed. believe me, it has been noticed! i've been telling friends who aren't even verilog users :) -dan
- Re: gEDA: Icarus Verilog 20010728 Snapshot mcmahill
- Re: gEDA: Icarus Verilog 20010728 Snapshot mcmahill
- Re: gEDA: Icarus Verilog 20010728 Snapshot Stephen Williams
