HI, first off, I don't know a defacto standard either.. On Tuesday 02 July 2002 06:16 pm, Stephen Williams wrote: > It gets worse:-O > > > The attributes parsed by the compiler are accessible to code > generators that use the ivl_target API. Thus, code generators > can define their own new attributes, if desired. I already used > this feature to allow the fpga target to accept pin assignments > from attributes in the source Verilog.
[jg]Was that a Silent Scream I heard? :-O [jg]At least it's an open API. Thanks! Are you concerned with the layer, layer, layer complexity of it? Verilog is good for reducing the "inline-sequential-code" to being invisible... that is it's true value. Any situational difference you desire to the way it works had better be made "practically invisible in a rock solid way" or else you are more prone to "human error". So, without knowing much of how you do it, the useful goal seems to me to be to make any "way it works" attributes go through the various possible layers with no functional change, or generate a message to the effect they are being overridden... John Griessen ++++++++++++++++++++++++++++++++++++++++++++++ [sw]The problem with synopsys style controls is that they apply to code, and not to syntactic elements. [sw]I would like to dream up a whole set of attributes that can be applied to processes to for example assure that a process is asynchronous, that it is synthesizeable, that it is not synthesized, etc. But if there is a defacto standard (that doesn't make me ill) then it would be good to try and follow that.
