I've spent some quality time with my copy of Xilinx Foundation, and I've got the Xilinx Virtex code generator in much better shape. I think the synthesis for this target at least is good enough for a 0.7 release.
The same goes for the feature set throughout Icarus Verilog, so I'm more or less starting a feature freeze and I'm looking to chase down bugs in preparation for the release. I've got a backlog of bug reports, but don't let that stop you from submitting more reports. Anyhow, here is the latest snapshot: <ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20021102.tar.gz> <ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20021102.txt> I've also got precompiled binaries for RedHat alpha and i386, as well as the source rpm for those who want to --rebuild packages for other targets. Get them here: <ftp://icarus.com/pub/eda/verilog/shapshots/precompiled/> I'll probably make a Windows binary as well in the next few days. Stay tuned. Release Notes for Snapshot 20021102 The big change in this snapshot has been Xilinx virtex synthesis support. It is now much improved, and there is a new examples/sqrt-virtex.v example that steps users through the task of making a chip from Verilog source to routed design. I've fixed a few named event scoping bugs. Some people reported problems with referencing named events by hierarchical names. These should be fixed. A few other bug related to error handling have also been fixed. The vvp simulation runtime lacked support for get vpiVectorVal values in a few contexts. I fixed at least one case, get from constant values. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." [EMAIL PROTECTED] [EMAIL PROTECTED]
