Here is my take on the subject.
1. Components --- devices that are often (usually packaged) have charateristics that should not be ignored at the schemtic design level.
Issues:
Device susceptibility to soldering temperature.
Is the device Pb free?
Does the device package match the thermal characteristics of the fab plastic?
For information about the device package we look to the JEDEC standard JEP95
But JEP95 has package families that are physically similar but made from different materials. For example Plastic Leadless Chip Carrier (PLCC) (JEP95 MO-047) and a Ceramic Leadless Chip Carrier (LCC) (JEP95 MO-044). Both include 0.050" pitch 68 pin leadless devices that would fit the same land pattern.
2. Land patterns are also dependent on the assembly solder method (wave solder, solder bath, reflow oven). IPC-SM-782-A "Surface Mount Design and Land Pattern Standard" includes a note in section 8.1 that states "If a more robust pattern is desired for wave soldering devices larger than 1608 [603], add 0.2mm to the Y direction and consider reducing the X dimension by 30%. Add a "W" sufix to the number e.g. 103W".
The number is the Registered Land Pattern Number of which a 103A pattern is the normal pattern for a 3216 [1206] chip resistor.
Proposal:
Symbols for gschem should not include the land pattern they should include the package identifier. The package identifier should be from the JEP95 or other consortium (European or Japanes) which ever is relevent for the device. I would also like to see the gschem symbols contain information about Pb content. Gschem should also have a way of showing the user what the package is and if it contains Pb in the preview mode while selecting devices from the library.
The netlist generator should translate the package identifier to a land pattern identifier based upon the assembly soldering method (normally reflow for surface mount). The land pattern identifier should be from a standard such as IPC-SM-782-A.
Steve Meier
