As for "performance" just remember the bad old days of C compilation?????? Now it may have taken us (collectively) a year to "pursuade" you ;-) but the current incarnation is a very usable product that has wide applications already. In pure behavioral simulations you are within striking distance of XL -and it sounds like some of the stuff you're talking about here will help in gate level sim performance.
Keep up the wonderful work!
Steve
Stephen Williams wrote:
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Maybe I should have been brainstorming this in public sooner:-?
Tom Hawkins wrote: | Stephen Williams wrote:
|> Where I'm headed is towards eliminating every pin array and creating
|> nodes for concatenation and select, and some type conversions. I'll
|> have fewer devices in a vvp netlist, all passing vectors/objects around
|> at run time instead of bits. As it stands now, I've been hacking at
|> the vvp engine itself to get a feel for what I want the generated code
|> to look like. I'll then be chopping up the compiler proper to handle
|> the new format. It'll be trial, experiment, and error for a little
|> while:-/
|
|
| This is how the Confluence backend is structured; with primitive
| elements for concat and select. The biggest drawback with this model is
| the added complexity for handling bit selection with tri-state buses --
| what if only some bits in a vector are tri-stated, while others are
| driven by a single source?
|
| For reference, attached is the set of Confluence logic primitives.
tri-stated bits are not an issue, as what gets passed around is vectors of 4-values. Any bits can have Z in them. Also, there will be no multiple drivers on a node of the graph, at least at the vvp level. Fan-out of a node is unlimited but fan-in at a port is always 0 or 1. Special resolver nodes will be used to manage strength resolution of multiple drivers. VVP does resolution that way already.
Also, some nodes will need to be type converters. The primitive types I currently have in mind are:
~ - scaler bits that carry strength information ~ - vectors that carry 4-values and no strength information ~ - reals that carry native doubles ~ - longs that carry native long integers
Almost everything will be done with vectors (even single-bit vecors) with
drivers converting one bit vectors to scalers and resolvers converting scalers
to one-bit vectors.
This seems simplistic, but really these types and the simple model of functors with 1 output and N (N <= 4) inputs can express most anything in the non-behavioral parts of Verilog. My white board has these functors drawn onto it:
~ vector = Arithmetic(vector, vector) ~ vector = Concat(vector, vector...) ~ * = Delay(*, long) ~ vector = PartSelect(vector, vector or long) ~ scaler = Driver/strength(vector) ~ vector = Resolver(scaler, ...)
I expect to add things on the fringes to fill in obvious blanks, and
munge the types a bit when things seem to not be working, but this is
the general idea, and a concrete picture that I can start hacking towards.
| It will take time. But in the end, you'll see a huge performance | improvement.
This is the goal. These days, performance is the biggest bug in Icarus Verilog:-)
|
| ------------------------------------------------------------------------
|
| (*
| Confluence System Design Language Compiler
| Copyright (C) 2003-2004 Tom Hawkins ([EMAIL PROTECTED])
|
| This program is free software; you can redistribute it and/or modify
| it under the terms of the GNU General Public License as published by
| the Free Software Foundation; either version 2 of the License, or
| (at your option) any later version.
|
| This program is distributed in the hope that it will be useful,
| but WITHOUT ANY WARRANTY; without even the implied warranty of
| MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
| GNU General Public License for more details.
|
| You should have received a copy of the GNU General Public License
| along with this program; if not, write to the Free Software
| Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
| *)
|
|
| (* Exceptions. *)
|
| exception Error of string;;
|
|
| (* Logic primitive types. *)
|
| type lp =
| | VecInput of string * int (* Params: name, width.
Inputs: none. Output: input. *)
| | VecOutput of string * int (* Params: name, width.
Inputs: output. Output: none. *)
| | VecInout of string * int (* Params: name, width.
Inputs: ctrl (drive output when high), data_out. Output: data_in. *)
| | VecAssert of string (* Params: message.
Inputs: assertion (message when low). Output: none. *)
| | VecPrint of int (* Params: width of print vector.
Inputs: enable, vector. Output: none. *)
| | VecConst of string (* Params: binary value.
Inputs: none. Output: constant. *)
| | VecBuf of int (* Params: width. *)
| | VecNot of int (* Params: width. *)
| | VecAnd of int (* Params: width. *)
| | VecOr of int (* Params: width. *)
| | VecXor of int (* Params: width. *)
| | VecConcat of int * int (* Params: width_left, width_right.
Inputs: left, right. Output: concatenation. *)
| | VecSelect of int * int list (* Params: width, bits selected.
Inputs: input. Output: output. *)
| | VecEqu of int (* Params: width.
Inputs: left, right. Output: equal. *)
| | VecAdd of int (* Params: width.
Inputs: left, right. Output: left + right. *)
| | VecSub of int (* Params: width.
Inputs: left, right. Output: left - right. *)
| | VecMul of int (* Params: width.
Inputs: left, right. Output: left * right. *)
| | VecSwitch of int (* Params: width.
Inputs: predicate, true, false. Output: selected data. *)
| | VecExtComb of string * int list * int * int (* Params: comp name, config params,
input width, output width. Inputs: input. Outputs: output. *)
| | VecExtSequ of string * string * int list * int * int (* Params: clock, comp name,
config params, input width, output width. Inputs: reset, enable, input. Outputs: output. *)
| | VecExtSoft of string * int list * int (* Params: comp name, config params,
width. Inputs: N/A Outputs: data. *)
| | VecTristate of int (* Params: width.
Inputs: ctrl, data. Outputs: bus. *)
| | VecReg of string * int (* Params: clock, width.
Inputs: reset, enable, signal. Output: register signal. *)
| | VecRom of string * int * Intbig.intbig list (* Params: clock, width,
values. Inputs: enable, addr. Output: value. *)
| | VecRamMem of int * Intbig.intbig list (* Params: data_width, initial values.
Inputs: none. Outputs: memory_link (not a real signal). *)
| | VecRamWrite of string * int * int (* Params: clock, addr_width, data_width.
Inputs: memory_link, enable, addr, data. Output: none. *)
| | VecRamRead of string * bool * int * int (* Params: clock, is_rbw, addr_width,
data_width. Inputs: memory_link, enable, addr. Output: data. *)
| ;;
|
|
| (* Misc. *)
|
| val bits : int -> int;;
|
|
| (* Primitive info. *)
|
| val primString : lp -> string;;
| val arity : lp -> int;;
| val width : lp -> int;;
| val inputWidths : lp -> int list;;
| val clockDomain : lp -> string;;
|
|
| (* Global settings. *)
|
| val setWriter : (string -> unit) -> unit;;
| val setEmbeddedC : bool -> unit;;
| val setExternalC : string -> unit;;
|
| val write : string -> unit;;
| val embeddedC : unit -> bool;;
| val externalC : unit -> string;;
|
|
| (* Misc functions for HDL code generators. *)
|
| val bytes : int -> int;;
| val intToBin : int -> int -> string;;
| val isCoded : lp -> bool;;
| val argList : string list -> unit;;
| val formatMsg : string -> string;;
|
|
- -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.0.7 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
iD8DBQFBilmcrPt1Sc2b3ikRAjwFAKC+1vVppJIu6ayBcWN+qyWCOOSgLQCfU100 NtZn8wEjkZYMDvVtQ0i9u+8= =c2dw -----END PGP SIGNATURE-----
-- Steve Wilson Hardware Architect GDA Technologies (408) 467-3595
