FNF is a flat netlist that retains hierarchical scoping. The netlist is a directed graph of primitive RTL operations, called cells. Some basics:
- All cells have 0 or 1 outputs.
- All cells operate on bit vectors.
The syntax definition is located here:
http://www.confluent.org/wiki/doku.php?id=fnf:main
(Steve, hopefully this aligns with Icarus synthesis, when you move it from bits to vectors.)
Shortly I will release an FNF generator for Icarus, followed by a Verilog, VHDL, C, and NuSMV writer.
Confluence Users, this should enable the following at some point in the future:
- Hierarchical HDL.
- 4-state C simulation models (01XZ), with VCD on all internals.
- Back annotation.
All comments are welcome.
-Tom
