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-- Cut here -- Delivery-Date: Thu, 04 Nov 2004 15:35:27 -0500 From: David Howland <[EMAIL PROTECTED]> I am getting the following output from iverilog: -------------------------8<------------------------- iverilog -tfpga -osimple.edif simple.v simple.v:8: warning: Process not synthesized. fpga target: unsynthesized behavioral code -------------------------8<------------------------- simple.v is a perfectly valid small piece of code, which will compile fine under other tools. When looking at the EDIF output, nothing is created but a hanging buffer, and all the outputs are left undriven. What is this warning telling me that I need to fix? Please reply to my email address, since I am not subscribed to the list. Thanks! -d
