Guys - I'm having trouble with Micron's DDR SDRAM model on Icarus-0.8. http://download.micron.com/downloads/models/verilog/sdram/ddr/256meg/256Mb_ddr.zip sha1sum 2009e8cef58b2d4247453c4f292b3f7c9633911b 256Mb_ddr.zip
Specifically, the first attempt to write bombs:
tb At time 2595.000 ns: WRITE Burst
At time 2599.000 ns WRITE: Bank = 0, Col = 10
At time 2610.000 ns WRITE: Bank = 0, Row = 0, Col = 10, Data = 10
At time 2610.000 ns ERROR: Positive DQS[0] transition required.
At time 2610.000 ns ERROR: Positive DQS[1] transition required.
At time 2614.000 ns ERROR: Negative DQS[0] transition required.
At time 2614.000 ns ERROR: Negative DQS[1] transition required.
I think I have isolated the fault to an actual incorrect waveform
for Dqs generated by the test bench, by task "write" in tb.v.
The intent looks like a tCK period square wave, but what actually
comes out is solid high. It looks like there is some time scale
confusion, I could get that part of the code to run in isolation
by changing from 1ns/1ps to 1ns/1ns. But then I get a bunch of
other errors.
I'll keep plugging, of course. If anyone else has tackled this
model, I'd like to hear about it.
- Larry
signature.asc
Description: Digital signature
