Hello,
I'm making some FPGA designs with Quartus II (tool from Altera) and I have a lot of
problems at synthesizing some cores from OpenCores.org. I am trying
iverilog to synthesise some module in the aim of using them as EDIF in
Quartus.
I have troubles at using this module blink.v (which successfully
synthesises under Quartus) and maybe have you some explanations. First, I synthesized it with: "iverilog -tfpga -o blink.edf blink.v",
which produced the EDIF file and the following messages as output:
blink.v:49: warning: Process not synthesized.
fpga target: unsynthesized behavioral code
fpga.tgt: IVL_LPM_CMP_EQ not supported by this target.
fpga.tgt: IVL_LPM_CMP_EQ not supported by this target.
fpga.tgt: IVL_LPM_CMP_NE not supported by this target.
fpga.tgt: IVL_LPM_CMP_EQ not supported by this target.
fpga.tgt: IVL_LPM_CMP_EQ not supported by this target.
fpga.tgt: IVL_LPM_CMP_EQ not supported by this target.
Then when I'm trying to use the the EDIF file under quartus, I have the
following error messages:
Warning: Can't locate Library Mapping File
Error: Can't find port "Result0" in instance "U42" of module "cell0"
Error: Can't find port "Result0" in instance "U40" of module "cell0"
Error: Can't find port "Result0" in instance "U39" of module "cell0"
Error: Can't find port "Result0" in instance "U34" of module "cell0"
Error: Can't find port "Result0" in instance "U34" of module "cell0"
Error: Can't find port "Result0" in instance "U32" of module "cell0"
Error: Can't find port "Result0" in instance "U30" of module "cell0"
Error: Can't find port "Result0" in instance "U35" of module "cell0"
Error: Can't find port "Result0" in instance "U35" of module "cell0"
Error: Can't find port "Result0" in instance "U36" of module "cell0"
Error: Can't find port "Result0" in instance "U24" of module "cell0"
Error: Can't find port "Result0" in instance "U25" of module "cell0"
Error: Can't find port "Result0" in instance "U27" of module "cell0"
Error: Can't find port "Result0" in instance "U29" of module "cell0"
Error: Can't find port "Result0" in instance "U29" of module "cell0"
Warning: Net "N61" has no sources. Ignoring net during synthesis.
Warning: Net "N66" has no sources. Ignoring net during synthesis.
Warning: Net "N71" has no sources. Ignoring net during synthesis.
Warning: Net "N74" has no sources. Ignoring net during synthesis.
Warning: Net "N78" has no sources. Ignoring net during synthesis.
Warning: Net "N79" has no sources. Ignoring net during synthesis.
Warning: Net "N80" has no sources. Ignoring net during synthesis.
Warning: Net "N81" has no sources. Ignoring net during synthesis.
Warning: Net "N82" has no sources. Ignoring net during synthesis.
Warning: Net "N83" has no sources. Ignoring net during synthesis.
Warning: Net "N84" has no sources. Ignoring net during synthesis.
Warning: Net "N85" has no sources. Ignoring net during synthesis.
Warning: Net "N103" has no sources. Ignoring net during synthesis.
Those messages refers to the lines from 200 in the EDIF file (blink.edf)
Find attach verilog core, EDIF output from iverilog and pdf from help of quartus talking around the problem.
I'm first writing to the mailing to know if someone as a solution. I'll post a bug report if it is one.
An other question is: why is the -t option for EDIF creation named
"fpga" and not "edif" ?
Fran6
