On Wed, Jun 29, 2005 at 10:10:34PM -0700, [EMAIL PROTECTED] wrote:
> There is (IMO) a slight problem with the view that it's OK to treat
> a continous assign the same way as a gate: while it makes sense for
> the case of "wire x = y & z", the degenerate case of "wire x = w" is
> perfectly realizable in hardware as a short-circuit and as such it
> shouldn't incur ANY scheduling delay (and thereby race conditions).
If the specs says there's a delay, it's a bug not to model a delay.
I actually know nothing about Verilog but the same behaviour exists in
VHDL.
x <= y and z;
x <= z;
Both of these result in a 1 delta-cycle delay (as it's known in VHDL).
Thus race conditions are possible. In particular you have to be VERY
careful when doing any assignments like this with the clock.
clk_delayed <= clk; -- 1 delta-cycle
process (clk)
begin
if rising_edge(clk) then
b <= a;
end if;
end process;
process (clk_delayed)
begin
if rising_edge(clk_delayed) then
c <= a;
end if;
end process;
In the simulator, this will NOT result in a 2-cycle delay.
In hardware it will.
Hamish
--
Hamish Moffatt VK3SB <[EMAIL PROTECTED]> <[EMAIL PROTECTED]>
