gEDA: Iverilog : problems with real numbers

[Steven Kwan]

Hi Steve and all,

Appreciate your effort providing Icarus Verilog to Verilog community.

I compiled and installed the latest Iverilog version 20060409 (after
trying stable release 0.8-1) and still got the following error message.

Below is the simplied pll_model.v file for your reference.

Thanks a lot for your help.

Best regards,
Steven.


/////////////////////////////////////////////////////////////////////////

[EMAIL PROTECTED] iverilog pll_model.v
pll_model.v:32: error: No function $realtobits in this context (pll).
pll_model.v:32: error: Unable to elaborate r-value:
$realtobits(filterVoltage)
pll_model.v:48: error: Real constants are not synthesizable.
sh: line 1: 19295
Done                    /usr/bin/iverilog-20060409/lib/ivl/ivlpp -L
-D__ICARUS__=1 -f/tmp/ivrlg196934e2
     19296 Segmentation fault
| /usr/bin/iverilog-20060409/lib/ivl/ivl -C/tmp/ivrlh196934e2
-C/usr/bin/iverilog-20060409/lib/ivl/vvp.conf -- -







/////////////////////////////////////////////////////////////////////////

/// File        : pll_model.v

`timescale 1ns/1ps      
`define SETTLINGTIME 42000

`define DIVCLKNOM 2.000000e-3
`define VCOCLKNOM 100.000000e-3

`define DIVCLKTOL 0.300000
`define VCOCLKTOL 0.250000

`define KVCOTYP 393.600000

module pll ( divClkin, 
         FBD,
         vcoClk, 
         filterVoltageBus);

input divClkin;        
input [7:0] FBD;

output vcoClk;
output [63:0] filterVoltageBus;

reg resetDone; 

wire resetDoneDelayed;  

real divClkPeriod; 
real vcoClkHalfPeriod;

wire [63:0] filterVoltageBus = $realtobits(filterVoltage);


initial 
   begin
   divClkPeriod = 1/`DIVCLKNOM;          
   resetDone = 0;
   vcoClkHalfPeriod = 0;
   vcoClk = 0;
   end

always @ (posedge divClkin) 
   begin 
   vcoClkHalfPeriod = divClkPeriod/((FBD+1)*2.0);
   end

assign #(6.0*vcoClkHalfPeriod) resetDoneDelayed = resetDone;

endmodule 

///////////////////////////////////////////////////////////////////