On Dec 20, 2006, at 8:34 AM, John Griessen wrote:
Kai-Martin Knaak wrote:
The symbol should be a
generic rectangle with all the ports of the schematic as pins.
Ideally
power symbols would also be included as pins -- ok, I stop
dreaming ;-)
This is something valuable that is available in chip design
software by Cadence and Mentor, and is very helpful for FPGA work
and even for some board layouts.
We need to dream one up, a gschem schematic to sub-schematic-symbol
genreating script, that is....
Agreed, this is necessary for board designs (I won't do an FPGA
design in a schematic). It's impossible to get even a small design
to fit onto one B-size sheet, considering how things are scaled in
gschem. (My little IR volume control design is three sub-sheets plus
a top level.)
I haven't sorted out exactly how (or even IF) gsch2pcb sorts things
out when a project has more than one page and no top-level sheet with
lower-level sheet symbols. My guess is that all net names are
global, and in-1.sym and out-1.sym (for example) are purely
informational. I also don't know if the DRC is smart enough to tell
you if an output on sheet A is connected to an output on sheet B.
Most of my board schematics consist of a top-level sheet that
instantiates a bunch of lower-level sheets. (On occasion a lower-
level sheet will itself instantiate an even-lower-level sheet.) Some
mechanism to automatically generate a "sheet symbol" would be very
useful.
Just as a reference point, Altium DXP has a "make sheet symbol from
subsheet" feature that looks at the sheet's I/O symbols and uses them
to build the sheet's symbol. Power and ground symbols are considered
project-global so they don't appear on subsheet symbols. You can
also configure DXP so that all nets are project global, so the
subsheet symbols and interconnects are purely informational. The
subsheet symbol stuff becomes a lot more useful when doing designs
with repeated channels (one schematic page is repeated N times and
the tool generates N unique instances of each component and net on
that page).
ANYWAYS, what would be useful is if there were special "page entry"
symbols (in, out, bidir) that take a netname attribute, and you'd
place this symbol on the page like any other symbol. A useful tool
could then scan the page and generate a proper sheet symbol with pins
named for and with the same sense (in, out, bidir) as the page
entries. A rectangle would be fine, with pins ordered as they appear
on the schematic, and they could be re-ordered in the usual ways
(gschem or a text editor). You then place the subsheet symbols on a
schematic, and wire 'em up. If we're not concerned with channelized
designs, then netlisting and DRC is straightforward.
-a
_______________________________________________
geda-user mailing list
[email protected]
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
