Hi, I'm very close to having my first EDA design ready for production. I'm currently trying to make the PCB Design Rule Checker accept the PCB layout without complaining.
There is one case where it complains about copper areas being to close, that I don't understand. Just look at the following screenshot: http://user.cs.tu-berlin.de/~dvdkhlng/clearance-problem.png The two pads are marked by the DRC as being to close. My DRC clearence is set to 0.15mm (about 6mil). But the two pads are more than 0.15 mm apart, as one can see by the black .15mm silk line that I managed to just fit between them. Maybe the DRC measures clearence only in X/Y direction of the pads, meaning for diagonal distance sqrt(2 * .15^2) mm would be required? best regards, David -- GnuPG public key: http://user.cs.tu-berlin.de/~dvdkhlng/dk.gpg Fingerprint: B17A DC95 D293 657B 4205 D016 7DEF 5323 C174 7D40 _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
