>>>>> "Dan" == Dan McMahill <[EMAIL PROTECTED]> writes:
> David Kuehling wrote: >> Hi, just another strange DRC error. This is caused by the >> oldlib-generated footprint "SMT_DIODE 15 8": Rules are minspace 5.92, >> minoverlap 5.91 minwidth 5.91, minsilk 7.09 min drill 1.00, min >> annular ring 15.75 Element Z50 has 5 silk lines which are too thin >> near location (1942.91,1350.39) Found 1 design rule error I thought >> PCB would just increase too thin silk lines when exporting gerber >> files. At least it does so for fonts... > It does not and I would object to it increasing too thin silk lines > automatically. Perhaps doing that causes silk on a pad for example. Thhe silk on pad thing is a real problem. On the other hand, auto-growing silk would help to abstract footprint library entries from specific vendor requirements... > My take is silk lines that are too narrow are real DRC violations. So then, what is the magick keycode / command to grow the SMT_DIODE silk line width? I tried the "Increment Lines by 0.10mm" menu item but without success. regards, David -- GnuPG public key: http://user.cs.tu-berlin.de/~dvdkhlng/dk.gpg Fingerprint: B17A DC95 D293 657B 4205 D016 7DEF 5323 C174 7D40 _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
