On 4/3/07, al davis <[EMAIL PROTECTED]> wrote:
One more point ...Node names are case sensitive. I suppose I should change it, but that part of the code is planned for major rework anyway, and Verilog is supposed to be case sensitive.
I'm a 20 year Unix veteran. I prefer case sensitivity :-) --wpd _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
