On Fri, Apr 06, 2007 at 05:57:32PM -0400, [EMAIL PROTECTED] wrote: > > Here are the results from > (1) Large reg (byte) array : reg [7:0] data > [0:sizeImage-1]; // sizeImage = 640*480*3 bytes > (2) Large reg vector : reg [sizeImage*8-1:0] data;
In the spirit of, "the implementor must cheat, but not get caught", it sounds like iverilog should detect the absence of continuous assignments and rever to an addressed model for the memory. A less general solution would be to infer addressable RAMs from templates as other synthesis tools do. -- Ben Jackson AD7GD <[EMAIL PROTECTED]> http://www.ben.com/ _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
