Adam Megacz wrote: > Stephen Williams <[EMAIL PROTECTED]> writes: >> The v0.8 releases of Icarus Verilog have decent synthesis. The >> synthesis is not at all Xilinx specific, but the code generators >> are. But they needn't be. The FPGA target generates EDIF, so if >> your intermediate form takes EDIF, the way to move forward is to >> work on the fpga code generator to generate code for your device. > > Hey, thanks for the advice. I've got 0.8.4 generating EDIF that > parses and flattens it into a netlist my PAR tools can handle. > > One difficulty, though: the primitive cells that iverilog emits are > pretty complex. Is there any way to ask it to break down multipliers > and adders into stuff no larger than a LUT4?
The reason it generates at that level is that in some cases it is the appropriate level. For example, there *are* multipliers in many modern FPGA primitive sets. It is a whole lot easer for a code generator to break down a multiplier into gates, then to merge up gates into a multiplier. > Also, what's the difference between the tgt-edif and tgt-fpga > directories? Licensing, mostly. The tgt-edif target source code uses a BSD style license, whereas the tgt-fpga target (which is currently a superset) uses the GPL license. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
