Hello :) Currently I am trying to port the Verilog code of the T1 and S1 to a user defined configuration of the processor ( # of cores, # of threads, etc ) written in Atom ( see http://funhdl.org/wiki/doku.php/atom ). I want to do this to aid in the SoC designing steps, that most embedded engineers are taking, through providing output of both Verilog and VHDL from the same source code, in addition to having the benefits of writing in a language more abstract than either of the HDLs currently available. I am a beginner in the EDA field, however, I certainly have time to contribute to learning and implementing. First, I went through both trees of code, and I have made a small outline of all the needed functions (remember outline, not even pseudocode, just placeholders) and now I am getting the `reset controller to wake up all the cores' function going. However, as I want to make this project fitting to a user specification, I do not know how the `constants' defined in the S1 core code compare to the official T1 branch for setup. I do not know how to calculate all the timer defines for the reset controller in each case of 1 core through 8 cores, and having multiple threads per core.. That is not really enough information to get a decent reply, I know, but all I'm looking for is someone who might be able to help me maybe (if time permits) by email, IRC (#geda), or something else. Basically I have just really small questions about Verilog and EDA that I don't want to `spam' the list with; questions that I have spent days trying to google without answers. Thank you for reading.
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