On 10/5/07, Randall Nortman <[EMAIL PROTECTED]> wrote: > I've got a tiny little 100-pin 0.5mm pitch TQFP chip that needs a > whole lotta I/O connected to it. I'm doing a 4-layer board (internal > VCC and GND planes), but I'm still getting all tied up in knots, with > vias all over the place. The connections tend to go off in different > directions -- these aren't pretty 16-channel busses. Anybody have any > general tips for dealing with this?
I usually do a rough placement of the decoupling caps first outwards of the chip. For the vias I alternate them inwards and outwards of the chip so that they fit. > One thing that would help would be if I could use the internal VCC/GND > planes for routing the odd trace or two, but I have heard that it is a > bad idea to run traces through the planes. Anybody have any thoughts > on this? It depends on how badly you breakup the plane and what frequency you are working with. A small trace or two that is surrounded by copper plane may not affect your circuit. Traces near the edge (outside the plane area) could work as well. As Bob said six layers does not cost much more than four. You may want to consider going to six. (* jcl *) -- http://www.luciani.org _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
