John Doty wrote: > On Dec 6, 2007, at 2:46 PM, Steve Meier wrote: > >> As long as its semantics is well enough deffined that I can write a >> macro to read and write its file formats then why not? > > It might be nice, but who knows what it is, and how to reasonably map > it onto our problem? Al's always selling Verilog. But I went and > bought the book he recommended on Verilog-AMS, and it was mostly more > sales pitch. > > I AM REALLY TIRED OF THE VERILOG SALES PITCH. > > Is there any *substance* here beyond the digital HDL? > > Al, *show* us something *real*. I don't necessarily mean you need to > write something: a pointer to something would be just fine (as long > as it's not just more pitch). But the more you push what seems to be > vapor, the more I'm going to ignore it. And I suspect I'm not the > only one...
I use verilog-A quite a bit and it is a huge benefit to me in real world (not just CAD vendor white paper) applications. Here is a simple example. You can generate a much more complex stimulus to drive a circuit under test with. Yes you could use <insert external program name here> to generate piecewise linear source, but it really can be much more convenient to have it integrated with the simulator. Also, suppose the source needs to react to some signal in the test schematic. PWL sources don't do that. Verilog-A does. Before I had access to AMS, I had several cases where Verilog-AMS had exactly the missing feature I needed to greatly simplify and expand some simulation coverage. I think a big part of the issue here is this: - there are no verilog-AMS implementations which are freely available or even priced in the few thousand dollar range. - there are no verilog-A implementations which are freely available. I'm not sure if you can get one for a few thousand or not. The end result is unless you're spending 10's of thousands on CAD software, you don't have access to these tools and as such people are not using them for hobby projects. Since the projects using those tools are all proprietary, there is little opportunity for users here to give much more information beyond "these tools are worthwhile". No concrete examples. Besides, its not like most people here could run a concrete example anyway because of the lack of an implementation that is even in the "pretty darn expensive but I want one at home anyway" price range. I could spend time an put together a non-proprietary example, but it would be a fair amount of effort because to fully appreciate the capability you need a problem of some complexity. And then at the end of the day I'd have an example that can't be run until gnucap has verilog-A or verilog-AMS. I for one am thrilled at how much Al is working towards having that capability. -Dan _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
