Hi, I am looking into using Icarus Verilog with Teal/Truss, a C++ based verification framework.
http://trusster.com/ Actually, to be more precise, Truss is the verification framework written in C++ and Teal are some utility classes, allowing to connect Truss to Verilog simulators via the PLI interface. The basic data type in Teal that does the PLI access to the simulator is the vreg class. There is a simple test that uses some vreg instances and connects them to a wire and a reg in Verilog code. The test is here: http://svn.trusster.com/tracker/repository/file/teal/trunk/cpp/test/vreg_test.cpp and the respective Verilog code is here: http://svn.trusster.com/tracker/repository/file/teal/trunk/cpp/test/vreg_test.v With Icarus 0.8.6 all tests but the last, with release of a_wire, are working. I went through the Teal code and what it boils down to is a vpi_put_value() call in connection with a Verilog wire type and the flag vpiReleaseFlag set. So the test is as follows: VERILOG: wire [5:0] a_wire; pullup (a_wire[0]); pulldown (a_wire[1]); In Verilog a_wire is created, with one bit being pulled up, another being pulled down. Then Teal connects to that wire and changes values and at the end calls the release function: TEAL: vreg a_wire ("top.a_wire"); a_wire(0,0) = reg (reg::Z); a_wire(1,1) = reg (reg::X); a_wire.release (); The expected outcome is that a_wire takes on its original value, assigned in the Verilog code (6'bzzzz01), but instead it is 6'bzzzzxz. The development snapshot has the same problem, but in addition the shown a_wire(0,0) = reg (reg::Z) assignments don't work. I searched through the bug-tracker and found issue # 1652096 vpi_put_value to net doesn't work Sounds like that this bug report describes the problem I am seeing with the Teal vreg_test. Is that a bigger issue to solve or is there someone working on its solution already? Now concerning vpiReleaseFlag I tried to create a simple test that triggers that behavior, but have a problem with the release. What I did is take a systemtask function from the Sutherland PLI book and changed it to write a value in the calltf function: ... s_vpi_value v; s_vpi_time t; s_vpi_vecval vecval; t.type = vpiSimTime; t.low = 0; t.high = 0; vecval.aval = (PLI_INT32)0; vecval.bval = (PLI_INT32)0; v.format = vpiVectorVal; v.value.vector = &vecval; vpi_put_value(vector_h, &v, &t, vpiForceFlag); //vpi_put_value(vector_h, &v, &t, vpiReleaseFlag); My original idea was to add the vpi_put_value with the vpiForceFlag and the vpiReleaseFlag right after one another. But that is not correct, as they appear at the same simulation time. Now I was looking for a simple way to advance simulation time and then issue the vpi_put_value call with the vpiReleaseFlag. It seems like I need to do that with a callback function that gets called at a specific simulation time. Does anyone know a simpler method to issue the vpiReleaseFlag call a time step after the vpiForceFlag call? Thanks for your help and sorry for the lengthy explanation. Cheers, Guenter _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
