On Sun, Feb 03, 2008 at 01:26:40PM +0000, ST de Feber wrote: > > The device in mind is an Altera Cyclone-3 FPGA. > Most probably the ep3c5.
My board has an EP2C8. Assuming you have a single IO voltage plus the core you can do this in 4 layers. I had GND and 3.3V on the planes. The 1.2V is made from 3.3V near one of the corners and a big fat trace on the top layer goes in the corner and around the perimeter of the chip. Almost all of the decoupling is underneath. The PLL voltages are made with caps+beads from the core voltage. Read the datasheet carefully because modern FPGAs have many rules for special use pins. -- Ben Jackson AD7GD <[EMAIL PROTECTED]> http://www.ben.com/ _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
