If I use pcb to make conductive traces, one thing I need is an insulator layer that does not fill in vias. The closest thing I see is outline layer behavior. When outline is exported the vias are not part of that layer. The layer I called insulator exports as the polygons I drew on it, plus all the via circles.
I found a sort of workaround -- if I put a square polygon with keepaway defined, I get the square and unrelated vias. If i move a square like that to outline, I get a square with semicircles cut out of it like I want. A small pcb file and screenshots of gerbv showing situation are here if you feel like a quick look: http://ecosensory.com/geda/ cond_ink_test.pcb cond_ink_test1.png cond_ink_test2.png cond_ink_test3.png group2 in the gerber output is for conductive ink that connects to top copper, unless insulator paint is in the way... When exploring different exports with gerbv ad gv I noticed the postscript differed. a polygon on layer 6 named outline also was output on layer 5 with the original polygons in postscript, but in gerber output that polygon was only on 6 (as it is defined in pcb) John Griessen -- Ecosensory Austin TX _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
