al davis wrote: > On Friday 25 April 2008, Stephen Williams wrote: >> As you know, this year's Icarus Verilog GSoC candidate is >> working on a VHDL code generator back-end for Icarus Verilog. >> Hooray! But suddenly the obvious question comes up, "How are >> we going to run these generated files?" I'm here looking for >> suggestions. > > What you need is the ability to translate the other way too. > That way, you can go around the loop and see if you get > equivalent Verilog back. > > Going both ways has another obvious benefit. We would get real > VHDL support too.
I fully agree. That would be awesome if along with the Verilog->VHDL converter there would be a VHDL->Verilog converter for the same feature set. When converting Verilog code to VHDL, chances are that there is a test bench already available in Verilog. So instead of converting this test bench as well, it would make more sense to keep that test bench and verify the VHDL based on the converted Verilog code. However, I do understand that in order to get matching Verilog->VHDL relationship there is the need during development to verify VHDL. I am not sure whether this fits here, there is Python project called MyHDL and it allows to convert Python code to Verilog. With the latest development snapshot the author Jan Decaluwe added a conversion from Python to VHDL. You can read about that under: http://myhdl.jandecaluwe.com/doku.php/dev:whatsnew:0.6 With the toVerilog conversion, co-simulation trough the PLI interface is used to verify the created Verilog code with the Python test bench. With the toVHDL conversation he could not use co-simulation and instead did some toVHDL conversation of the test bench code as well. Maybe his thoughts are of some help here. You will also find posts on comp.lang.vhdl from him about problems he ran into with the toVHDL conversion. That might be of some help for the student working on the VHDL converter. Now, Jan did not go that route, but, GHDL has some PLI interface support. It seems like there has been some work in ADA on that, but there is also some C or C++ code for that. At least I was reading about that in the GHDL mailing list archive some time ago. There is a IEEE paper about using GHDL in connection with SystemC via the PLI: "A Methodology and Toolset to Enable SystemC and VHDL Co-simulation" Maciel, R.; Albertini, B.; Rigo, S.; Araujo, G.; Azevedo, R. VLSI, 2007. ISVLSI apos;07. IEEE Computer Society Annual Symposium on Volume , Issue , 9-11 March 2007 Page(s):351 - 356 Maybe that is of any help here. Cheers, Guenter _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
