> The latter one have a strange behavior. The most problematic that some > of the lines not clears the rectangle used for filling the unused area > by copper. Unfortunately DRC does not show any error or warning although > there a many short circuit due to the rectangle.
Looks like a bug to me. Ben? Can you look at this one? > Additionally the copper (size: 0.1mm, 0.1mm, w-0.1mm, h-0.1mm) surrounds > the mounting hole in case of the control.pcb, but not for the io.pcb. Use the thermal tool to change that. > Furthermore am I right that ClrFlag(selection, join) should switch on > clearance for all selected lines? But it seems it is not working for me. It should. _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
