On Thu, 2008-06-26 at 15:22 -0700, Ben Jackson wrote: > On Thu, Jun 26, 2008 at 11:07:49PM +0100, Peter Clifton wrote: > > > > This is similar to the code in the Xilinx I2C entity. > > > > When I try to assign from the input port of the IOBUF using similar > > code, I just end up getting this error. > > > > http://www.xilinx.com/support/answers/14264.htm > > Right, FPGAs don't really have internal tri-state (or wired-or) busses. > If you had two I2C modules connected to the same pins, the I/O/T model > allows you to combine them at one output. If the module just took 'SDA' > and did the tri-stating internally then I would expect you to get that > error when you connected another I2C module.
Actually, its physical pins on the device I'm wanting to connect it to. The code was designed for a CPLD, so perhaps there is a difference. In ISE, with the FPGA I'm putting down buffer symbols which tell it what kind of IO to use. If you could directly map the "INOUT" port to a pin on the chip (where "0" or "Z" output states would make sense), that works intuitively. What I couldn't do was take the inout lines, and connect them to the outside world via an IOBUF. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
