Thanks John D., John G.! I've just tried it and it is OK. Anyway it still is a bit strange that some elements are doubled and some not, but I had wrong project file. Mant thanks once more.
> If you have a big main sheet, yes. This causes gnetlist to spend a > long time tracking down connections (the algorithm appears to be O > (n^2)). One of the drawbacks of the big main sheet approach. I generally don't like schematics that are too much split - I need to spend too much time tracing connections by names :-). Anyway in this project if I wanted to have smaller sheets I would have to place one IC on one sheet. I set up makefile to do drc, netlist, pcb, (thanks to gEDA design that I really like) and waiting is normally not a problem, because I can run it in background still working on schematic or pcb. Best Regards, Michael WIdlok Dnia 20 września 2008 16:49 John Griessen <[EMAIL PROTECTED]> napisał(a): > John Doty wrote: > > > You shouldn't give the name of the subsheet directly to the > > netlister: it finds the subsheet through the source= attribute. By > > giving the name explicitly, you told gnetlist to include the > > subcircuit at top level, and by using a symbol with a source= > > attribute you told gnetlist to include it as a subcircuit also. So, > > you got it twice. > > > That's it, John D. found the reason, no bug to look for. any netnames > youhave in your subsheet will get S11/ prepended to them and so they > will not make a connection except through the source= method. > > John G > > _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
