On Sat, 2008-09-27 at 22:44 -0700, Ben Jackson wrote: > Projects with microcontrollers and FPGAs often have a lot of flexibility > in how things get connected. My workflow for those projects is to build > a sparsely connected schematic and then move to PCB to explore geometry > options. Once I see what will be easy to route in PCB I start making > connections based on the physical layout. Sometimes I do this by picking > a starting pin and assigning them sequentially in gschem (FPGAs make this > fairly easy, at least with "linear" packages). Sometimes I use 'D' and > 'Shift-D' to annotate pins or bring up the whole package in PCB so I know > which pins I can consider and then just route them (with auto-DRC disabled, > kind of a bummer) and use the conflicts to back-annotate the PCB.
I've considered that some kind of structural VHDL / verilog file might actually be a good "origin" format for this kind of workflow, where the "truth" of the connectivity is stored in a .vhdl style file back-annotated from PCB. The VHDL would then be able to perform the arbitrary mapping from the nets attached to the corresponding symbol in the schematic, to the PCB board. E.g. my FPGA symbol is abstract, has pins / (buses in future) for _functionality_, and a "source=fpga_foo.vhd". That VHDL file would then map the package pins, onto the ports exposed by the symbol. You could also write a tool to take the .vhd file and emit a schematic which attahches named nets / busrippers + netname=... attributes. to the pins of a symbol representing the real pins on the FPGA package. Since I'm not a geometry guru, I'd probably start by making a template schematic with "netname=?????" or something similar, then teach gnetlist / a new tool to find those and replace them from the back-annotation. [snip] > Any ideas for how to express a "meta rat"? How to visualize it? How to > specify it in gschem, in a netlist, etc? That sounds like it is derived from a much more expressive description of "gate"-swapping available for the part. I can't see how you can visualise it for more than one net at once, but for example.. let me tell PCB I'm routing rambus_d7 (either by selecting it, or picking it from a list). I'd have that net selected / lit up somewhere in PCB, and the rules-processing should light-up the possible pins I can wire it to. (This would also make another potentially nice visual hint for drawing nets which just have one valid destination). > Any better ideas for how a line drawn in PCB could be automatically driven > back to a schematic? Perhaps as a "rat" in gschem?? This is basically how I want to see at least some kinds of back-annotation handled in gschem. As yet, gschem doesn't support much concept of a netlist internally though, so -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
