I am getting almost random behavior with the PCB Design Rule Checker. The problem occurs on a double side board with 3 SMT caps on the back side of a 44-pad SMT CPU chip. I can place the caps and vias without problem. After placing each trace from cap/gnd to via the DRC is run. Once the third trace is drawn the DRC fails on all three. Removing the last drawn trace does not restore to previous DCR results. Removing all 3 removes the DRC messages.
Errors message indicate trace too close or possible broken trace. "Optimize Rats Nest" seems to be working ok. However, "Autoroute All Rats" reports a stale rats nest. Plotting the trace does not show any visible problem. Fedora 8, PCB version 20081128. Regards, George _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
