> I'd like to add some non-silk graphics to my pcb layout (Dimensions > of a cooler). I added a separate layer for this purpose. However, > lines put in this layer are interpreted as copper when crossing vias > or pads. This confuses the generation of rats. Is there a way to > make a layer completely insensitive to all connectivity operations?
Not at the moment. _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
