On Jan 14, 2009, at 2:06 PM, Joerg wrote: > Steven Michalske wrote: >> Hey gang, >> >> This is a proposal that seems to have gotten lost in a debate if gEDA >> is the right toolkit for someone. >> >> So here is a technical discussion on how we could IMPROVE gEDA. >> >> The proposal, please comment on lapses of functionality, and one >> sidedness as I use gEDA in PCB and spice 'n friends workflows >> >> >> When adding a slotted or multi part component it should have an >> attribute of an unique instantiation ID (UIID) that gets matched With >> the other symbols of that device instance. >> - have a ui pop up with this is a slotted/multi part device, >> - have options to add to existing instance, add new, or save for >> hierarchy compilation >> - have options for specific slot, next, undecided, or best slot >> >> This works into deeper capabilities, assisted slotting and multi >> symbol verification. >> >> To make slotting more robust to errors like U1a and U1b both having >> slot 1, >> To make sure that multi symbol parts have all their symbols, such >> as a >> microcontroller missing one of it's three sub symbols, it would warn >> the designer >> >> it should match each slotted device with it's UIID >> it should verify that each UIID is complete to it's devices rules. >> - i.e. a device of type X has the symbols of: one power >> symbol, >> one >> foo symbol, and one foo+power symbol. >> - There can only be upto 4 foo slots > > > Not sure what foo means in this context but anyhow, the max number of > slots for a library part should be kept high. Bus drivers, HV drivers > and such can have dozens.
this was meant as a specific example, not a defined max in the implementation. > > > >> - there can be only one of the 4 foo slots with power. > > > Sometimes there can be parts where supplies are split between two or > more dies inside a package (multi-chip like). But this is very rare. interesting point...., a non rare case would be bank powers on an FPGA > > > >> - There must be one power connection > > > Some parts do not have a power connection at all. For example resistor > arrays or diode arrays. this is an example of a specific device X that has 4 slots of foo with one power connection method. those examples would not have a power sub symbol. > > > >> - Spare slots should have a default connection scheme. >> slot pin 1,2,3 should be tied to GND of the power for >> this UIID, >> pin 4 to VCC, pin 5 is NoConnect >> - etc... >> - Hate to say it, but sounds like a data base :-P >> - ok an additional file type, *.msym for meta symbol. >> >> it should renumber a UIID to the same refdes. >> it should verify that a UIID is not over spent ( i.e. 5 slots on a 4 >> slot part ) >> >> it should list an under spent UIID >> - This would allow for post netlisting combinations. example in a >> design you have 16 sub modules that use 2 of 4 slots in a part, >> half >> of each share the same power nets, we should assist the collecting >> of >> the parts with the same power ground nets. >> - e.g. printout, or pop up a slot editor. with the following info. >> refdes U1, U2, U3, and U4 have spare slots and share the same power >> and ground >> >> This would require the schematic to physical stage to have a slotting >> tool that understood this. >> - this stage could output a slotting information report that PCB or >> other layout tools (humans) could read. >> - PCB could then allow for back annotating slot changes with the >> help of the report >> >> we should drop the refdes+letter notation going forward. >> - The suffix should be generated not defined as part of the refdef >> - I don't want U1a to point to the first slot then in U2a points >> to >> slot 3, unless you tie them together two locations can conflict/ >> confuse. e.g. a technician is debugging a part, they have worked on >> three stages, but each part calls it stage?/U1A well unfortunately >> each section being differently laid out had U1A being different >> slots. making shortcuts that are often taken they measured the wrong >> pins, because a b and c were pins 1 2 and 3 on U1 but 3 2 and 1 on >> U2. >> > > Just my 2 cents, but this should be defined in the library. For > example, > pins 1,2,3 of a particular opamp is always U?A, pins 5,6,7 is U?B > and so on. In my imagination, the a b c would have been defined in the meta symbol, connecting them to the same pins would be good for locking them down. > > > -- > Regards, Joerg > > http://www.analogconsultants.com/ > > > > _______________________________________________ > geda-user mailing list > [email protected] > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
