Larry Doolittle wrote: > On Sun, Mar 08, 2009 at 06:41:31PM -0400, DJ Delorie wrote: >>> is there any type of regression test suite for PCB? >> Nope. > > That, itself, sounds like a bug. > > - Larry
It is, but I've never felt like I had enough of a clue on how to start writing one for pcb to get there. I did have a vague notion of wanting to start working on some small layouts that probed the boundary conditions for DRC and connection scanning, but I never quite figured out the framework for how this was run. I could also envision something that took designs, produced RS274-X files and let gerbv load them and XOR against a verified RS274-X file. As far as a pixel by pixel xor of png outputs, that is what we do for gerbv. We load files, export to png and do a pixel xor against reference png files. Problem is due to minute differences in numerical roundoff between various hardware involved, the testsuite complains loudly on many platforms. Enough so that I tend to generate a new set of reference png files, apply my source code changes, and test against my private reference files. At least that way I can detect a change. It would be good to make that testsuite more robust though. -Dan _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
