The simulated annealing or however it's called sometimes > produces awful placements (and I had less than 1% of the chip > used, an XC3S200A-FT256). Floorplanning can help a lot > in these cases. > > Gabriel
I would refrain from floorplanning on small designs. Are you using a constraints file? You just need to set the constraints properly - it usually works pretty good. The trick is writing good constraints. ISE will tell you if it exceeds your constraints. Also, I'm pretty sure you can tell the synthesis tools and PAR tool that you want to use IOB flip-flops. Personally, I don't like to write verilog code with manufacturer specific constructs - it's not portable. _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
