2009/5/8 Eric Brombaugh <[email protected]>: > John Griessen wrote: >> How about the code intensive hardware system developers that start >> a project with FPGA then migrate it to ASIC? What language do they use -- >> c++? > > Typically they'll use a HDL like Verilog or VHDL. Those are generally > compatible across FPGAs and ASICs alike. There have been attempts to use > C++ for hardware design, but they haven't found their way into the > mainstream.
Indeed, C/C++ tends to be very domain-specific (usually DSP). I'm sure that will slowly change. and there are plenty of FPGA designs out there that have been completely realised in Matlab. > > There are newer HDLs starting to find more use though - System Verilog > is becoming popular among some of my colleagues. <opinion>The penetration of SystemVerilog for Design is fairly limited in my experience - but for verification, it's on a very steep upward curve right now. I still see Verilog as being dominant for the next 5 years.</opinion> As for the original topic/question, I'm astounded that Tcl hasn't had more of a mention. In my day job, most EDA tools I use day-to-day are built around/have embedded a Tcl interpreter. Scheme is not on the radar. Cheers Gareth _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
