Just re-etched the outer layers. The last time, the traces ended up too thin and many of them etched through, yet other parts of the board had shorts. Go figure. After some testing, I got a setup that works (note that PNG has a "bloat" setting now too ;-). Results at the bottom of http://www.delorie.com/electronics/sdram/
So far, I've found only one defect - an easily repaired break in one of the traces on the MCU side. Yes, all those 6/6 serpentines etched correctly :-) Some close ups here: http://www.delorie.com/pcb/lab/ You can also see the results of a custom HID I wrote that sits between PCB and the PNG exporter. It checks connectivity on each of the four layers and adjusts the via patterns accordingly. For example, if I'm connecting layers 1 and 3, layer 2 has no copper and layer 4 has a target that means "drill out completely". If I'm connecting 1 and 2, layer 1 has an oval drill that means "drill bigger", layer 2 has no drill, and layers 3 and 4 have no copper. I'll pre-drill the outer layers, adhere the layers together, then drill all the through holes. _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
