This is really a strange bug. My nearly finished board has some design rule bugs, the first is a via too close to a trace on the bottom of the PCB, on the lower right side of the FPGA. I use Connects/Design Rule Checker and cancel the operation after this first bug is found. Fine, but now all my traces and elements are off grid. Strange and ugly.
If this is an unknown bug: The board is available at http://www.ssalewski.de/DAD.html.en http://www.ssalewski.de/b1.pcb20090906.bz2 bunzip, start PCB (20081128 GTK) with this board and select Connects/Design Rule Checker. Now traces and element centers are off grid. Best regards Stefan Salewski _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
