> Well, there is clearly a missing piece of data: mapping from logical > function onto package pin number.
I've talked about one solution for this, many times in the past... my idea is to tag the symbols with signal *names* and map the names to package/pinout via whatever does the gschem->pcb migration. That way, slotting and packaging are separate from the symbol, but can be encapsulated elsewhere (and perhaps back-annotated to the schematic). It also allows us to expose pin/gate swapping to pcb. _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
