On Dec 28, 2009, at 9:21 AM, Dave McGuire wrote: > > Such repairs would be pretty much impossible without the full > component- and gate-level schematics I have for these machines, of > which this is an example of one page: > > http://www.neurotica.com/misc/kb11c-117.png
You misunderstand me. That's a logical level schematic. Not a "physical" schematic, where the blocks on the page would be component packages. I don't see any component packages here. I think you would agree that a diagram that was all 14 and 16 pin boxes would me much harder to read than the "shovels and shields" style logic diagram that you have. Your schematic is exactly what I am advocating (well, except that I prefer ANSI symbols). What I think is useless is a diagram that is packages and pin-outs instead of function and logical flow. > > One or more high-level "logical" schematics, block diagrams really > form a sort of "table of contents" for the rest of the schematic. That's a block diagram. > The schematics are printed on 11"x17" paper. The ones for the > PDP-11/70 processor mentioned above are about 300 pages. Yes, PDP-11/70 is a lot of functionality in an impressively small package. 300 sheets is big enough to get lost in if it isn't well organized, but is still a small design. When I talk about making gEDA scale, I want the target to be designs 20x-50x larger. Not that I expect gEDA to take over as an enterprise-class EDA tool, but if people aim high it will lead to a more fundamentally sound design. -dave _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
