I use gEDA for small projects. One, and two sided boards only. It's been fine up until now. I now have a transceiver chip with some pins, a number of which I need to run to pin 1 on an IDE header. No matter how I draw the nets in gschem, the final rats nest runs produced in pcb is one trace, across all the pins on each side of the SOIC, as long as any of them are in the star end-run to the header pin. In other words, if I want to tie pins 1,3,5, of the transceiver, to pin 1 in the header, a rat route runs across pins 1,2,3,4,5, of the transceiver, shorting all of them together, and then routes to header pin 1. How can I separate these nets? Where do I do it? (gschem, gsch2pcb, just gnetlist, or pcb) My only solution, so far, has been to plant small terminals in each run in gschem, with a very small via footprint. This forces separate routes to pin 1 on the header in pcb.
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