Peter Clifton <[email protected]> writes: > On Sat, 2010-03-27 at 08:57 +0100, Stephan Boettcher wrote: >> gene glick <[email protected]> writes: >> >> >> This is the board: >> >> >> >> http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/erena/erena.pcb >> >> >> >> Any idea if it is a good idea to just ignore these violations? >> >> >> > >> > Blindly ignoring violations is probably not a good idea. Better to >> > understand them first. >> >> Well, I visually scanned the perimeter of the violating planes and did >> not find any problems, OTOH, Peter did see them, he said, so I need to >> look more carefully. > > I didn't verify whether they were in fact, too close, just that I could > make the violations go away by adjusting their clearances. It could be > that PCB is miss-calculating the gaps.
Ok. I will do that then, since there is no reason why they need to be so close (10 mils) in most cases, just to get my layout DRC clean before I submit them (on Monday?). But pushing things around without knowing why, is the first step into woodoo type work flows, which we got away from by not using proprietary tools any longer :-) > It is also possible that the points which get too close aren't actually > visible - are cleared away by vias / tracks - but the DRC check is > "imagining" what the polygon is defined to look like when checking it > against other polygons. I'm not 100% sure on that. Yes, that is what I first suspected too. E.g., where the FPGA core power lines go into the io-power plane that is locally cleared away by the vias. So I modified that to make those lines not join the planes, and put joining lines over the edge of the core power plane to cover the clearance of the via-connecting lines. This did not make the DRC happy. And yes, I was looking for this and other "imagined" clearance problems, but could not identify any remaining problem. Maybe I discover something when I now start increasing the clearances. Thanks! -- Stephan _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
